A semiconductor integrated circuit (IC) generally includes core circuits for performing certain functions and peripheral circuits for communicating the performed functions with external circuits. The semiconductor IC often has a dual gate oxide structure, because MOS transistors provided in the core circuits and peripheral circuits may have different requirements for thicknesses of gate oxides thereof. For example, an MOS transistor in a core circuit requires a very thin gate oxide (core oxide) to achieve a strong capacitive effect of the gate oxide and therefore good control over the channel region by the gate of the MOS transistor. In contrast, an MOS transistor in a peripheral circuit may require a relatively thicker gate oxide (I/O oxide) capable of sustaining a higher voltage applied to the peripheral circuit.
Because a leakage current through a gate oxide increases exponentially as the thickness of the gate oxide decreases, the thickness of the gate oxide of an MOS transistor cannot be decreased indefinitely. A conventional technique for improving control over the channel region by the gate of the MOS transistor is through plasma nitridation of the gate oxide to increase the dielectric constant thereof, as a result of which the capacitive effect of the gate oxide is enhanced and the control over the channel region by the gate may be improved.
A semiconductor IC also includes several layers of metals to provide contact among circuit elements of the IC and between the IC and external circuits. Inter-metal dielectric (IMD) layers are provided between the metal layers to isolate the metal layers from each other. To minimize the capacitive effect of the IMDs, thereby maximizing a speed of the semiconductor IC, it is often desirable to lower the dielectric constant (k) of the IMDs. Electron beams (e-beams) are frequently used to cure the IMDs to achieve low-k or extra-low-k (ELK) IMDs.
FIGS. 1A-1D illustrate a process of forming a semiconductor device 100 having a conventional dual gate oxide structure.
In FIG. 1A, a semiconductor substrate 102 is provided. A core area 104 is defined as a portion of semiconductor substrate 102 for core circuits. A peripheral area 106 is defined as a portion of semiconductor substrate 102 for peripheral circuits. A layer of core oxide 108 as a gate oxide of a core MOS transistor is formed on semiconductor substrate 102 in core area 104. A layer of I/O oxide 110 as a gate oxide of a peripheral MOS transistor is formed on semiconductor substrate 102 in peripheral area 106. As shown in FIG. 1A, I/O oxide 110 is substantially thicker than core oxide 108. A post-oxidation anneal in nitric oxide (NO) is performed to reduce interface states at the interface between semiconductor substrate 102 and core oxide 108 and I/O oxide 110.
In FIG. 1B, a plasma nitridation process is performed to increase the dielectric constant of core oxide 108 and I/O oxide 110. As a result, a portion 108′ of core oxide 108 and a portion 110′ of I/O oxide 110 are nitrided. Then a layer of polysilicon 112 is formed on core oxide 108 to serve as the gate of the core MOS transistor and a layer of polysilicon 114 is formed on I/O oxide 110 to serve as the gate of the peripheral MOS transistor.
In FIG. 1C, an inter-layer dielectric (ILD) layer 116 is deposited on polysilicon 112 and 114 and contact holes 118 are formed in ILD layer 116. A first layer of metal is deposited on ILD layer 116 and filled in contact holes 118, and patterned to form first metal patterns 120 to provide contact to polysilicon 112 and 114. An etch stop layer (ESL) 122 is provided on first metal patterns 120. An IMD layer 124 is provided on ESL 122 and is cured by e-beam to achieve an extra low dielectric constant, e.g., below 2.5.
In FIG. 1D, first vias 126 are formed in IMD layer 124 and ESL 122 by separate etchings of IMD layer 124 and ESL 122. A second layer of metal is deposited on IMD layer 124 and filled in first vias 126, and patterned to form second metal patterns 128.
Conventional steps may be performed before, between, or after the above steps to complete semiconductor device 100, such as formation of source and drain regions, formation of additional metal layers, and packaging, etc.
A problem associated with the above-described process for forming semiconductor device 100 is discussed below.
In the plasma nitridation process of core oxide 108 and I/O oxide 110, nitrogen introduced into core oxide 108 and I/O oxide 110 breaks Si—O bonds in the oxide and results in sub-oxide formation at the interface between semiconductor substrate 102 and core oxide 108 and I/O oxide 110. Consequently, traps are formed at the interface between semiconductor substrate 102 and core oxide 108 and I/O oxide 110, and a reliability of core oxide 108 and I/O oxide 110 is degraded.
During the subsequent e-beam curing process of IMD layer 124, beams of electrons are directed at IMD layer 124. The electrons may penetrate through IMD layer 124 and ESL 122 and accumulate at first metal layer 120 and later-formed vias 126.
The charge accumulated on first metal patterns 120 and vias 126 due to the e-beam curing of IMD layer 124 dissipates through vias 118 and polysilicon layers 112 and 114. In peripheral area 106, I/O oxide 110 is thick and electron tunneling does not occur. The charge accumulated on one side of I/O oxide 110, i.e., in polysilicon layer 114, coupled with the traps on the other side thereof, i.e., at the interface between semiconductor substrate 102 and I/O oxide 110, degrades performance of the peripheral transistor. For example, a leakage current, a threshold voltage, and a noise of the peripheral transistor may increase. Such damage caused by the accumulated charge is generally referred to as plasma-induced damage (PID) and sometimes as BEOL (back-end-of-line) PID. Here BEOL refers to the processing steps following the formation of first metal patterns 120, in contrast with FEOL (front-end-of-line), which refers to the processing steps prior to the formation of first metal patterns 120. In core area 104, because core oxide 108 is very thin, e.g., 10-20 Å, the charge resulting from e-beam curing can tunnel through core oxide 108 and is discharged at semiconductor substrate 102. As a result, the BEOL PID problem is less severe in core area 104.
As discussed above, due to the plasma nitridation process, semiconductor device 100, especially peripheral area 106 thereof, suffers a serious BEOL PID problem. To minimize the amount of charge accumulated on first metal patterns 120 and vias 126, the e-beam curing process of IMD 124 must be performed within a narrow processing window. If the processing window is so narrow that e-beam curing is impractical, alternative solutions for achieving extra-low-k IMD 124 must be found, which may delay production.
Depending on the dimensions of the first metal patterns 120 and first vias 126, the amount of electrons stored therein differs. FIGS. 2A and 2B respectively show the effect of the sizes of the first metal patterns and the first vias on the performance of peripheral MOS transistors formed using the above-described conventional process. In both FIGS. 2A and 2B, the peripheral MOS transistors formed and measured have a nominal operation voltage of 2.5V, the abscissa is yield, and the ordinate is the gate leakage current. The numbers 13, 14, 15, 16, 19, and 20 refer to batch numbers of the MOS transistors formed. A dashed vertical line indicates acceptable yield (approximately 95%) in each of FIGS. 2A and 2B. As shown in FIGS. 2A and 2B, a so-called tailing of the gate leakage current occurs above the acceptable yield, i.e., the gate leakage current increases significantly. Moreover, the gate leakage current is higher when antenna ratios (AR) are higher, wherein an antenna ratio is defined as the ratio of the size of the metal layer or the size of the via to the size of the gate oxide of the MOS transistor.